1. Field of the Invention
The present invention is related to a transistor circuit consisting of a plurality of metal insulated gate field effect transistors (hereinafter referred to as MISFET's). More specifically, the invention deals with a decoder circuit employed in a MIS static memory circuit.
2. Description of the Prior Art
A static memory circuit based on an inverter circuit of the ratio type does not require a complicated refreshing circuit for regularly refreshing the memory cells so that there is no extinguishment of the stored information in memory cells generally used in a dynamic memory circuit based on an inverter circuit of the ratioless type, and also does not require clock circuits for clock-driving the circuits surrounding the memory cells. However, a problem remains in that the static memory circuits consume a great amount of electric power as compared with the dynamic memory circuit. In driving the memory circuits, in general, a considerable proportion of the electric power is consumed by the peripheral circuits, especially by the decoder circuits.
When the static memory circuits are to be employed for the main memory portion of large computers, therefore, it is required that the decoder circuit consume a reduced amount of electric power during stand-by periods.
Here, the inverter circuit of the abovementioned ratio type determines the output level depending upon the ratio of the resistance of a load MISFET to the resistance of a driver MISFET, while the inverter circuit of the ratioless type determines the output level depending upon whether an electric charge accumulated in a capacitor is discharged or not. Therefore, with the inverter circuit of the ratioless type there is substantially no current pass between the power source and ground.
There are known static decoder circuits equipped with power switches T.sub.8 and T.sub.1 that are driven by clock pulse signals, as shown in FIGS. 1 and 2, such that the consumption of electric power could be minimized. During the operating period, the clock pulse signal acquires an "H" level (high level, V.sub.cc) to turn on the power switches T.sub.8 and T.sub.1. During the stand-by period, on the other hand, the clock pulse signal acquires an "L" level (low level, zero volt) to turn off the power switches T.sub.8 and T.sub.1.
Referring to the decoder circuit shown in FIG. 1, the power switch T.sub.8 is provided on the grounded side of a gate circuit composed of MISFET's T.sub.2 to T.sub.7. The power switch T.sub.8 is turned off during the stand-by periods. Therefore, a current pass between a power supply V.sub.cc and ground in the decoder circuit is interrupted by the power switch T.sub.8. However, the inventors of the present invention have analyzed the circuit and confirmed that the output signal level from the output terminal XN attains the "H" level, causing the MISFET's in a memory cell array (not shown) to turn on giving rise to the development of a current pass from a common load MISFET of the memory cell array to ground.
Referring to the decoder circuit shown in FIG. 2, on the other hand, the power switch T.sub.1 is provided on the side of a power supply Vcc of a gate circuit composed of MISFET's T.sub.3 to T.sub.8. Here, the power switch T.sub.1 is a MISFET of the depletion type of which the threshold voltage level is set at near zero volt. Symbol T.sub.12 represents a MISFET of the depletion type which compensates the level during the periods of long cycles or when the selection time has continued for long periods of time. It was, however, confirmed by the inventors of the present invention through circuit analysis that even the decoder circuit shown in FIG. 2 gives rise to the defects mentioned below during the stand-by periods.
(1) When at least one of the address signals fed to address input terminals (a.sub.0 to a.sub.5) is at the "H" level.
In this case, since the depletion type MISFET T.sub.1 is not completely turned off, an electric current flows from the power supply Vcc to ground through MISFET's T.sub.1 and T.sub.2.
(2) When address signals fed to the address input terminals are all at the "L" level.
In this case, an "H" level signal is applied to a point A, whereby a MISFET T.sub.10 is turned on. Therefore, an electric current flows from the power supply Vcc into ground through MISFET's T.sub.9 and T.sub.10.
Accordingly, the decoder circuit shown in FIG. 2 is not capable of completely interrupting the current pass during the stand-by periods.
It is therefore desired to provide a static decoder circuit which does not develop such a current pass and which consumes less electric power.